This invention relates to an all-stage direct-coupled amplifier, and more specifically to an all-stage direct-coupled amplifier capable of output offset regulation.
Prior art direct-coupled amplifiers employ various measures to reduce output offset voltage. The simplest approach to this problem is to provide a capacitor between a feedback input terminal of a first stage differential amplifier circuit and circuit ground. Such approach will, however, adversely affect the low-frequency response of the amplifier. Maintenance of satisfactory low-frequency response requires the use of a large-capacitance capacitor, which would cause unstable circuit operation.
An output offset regulator circuit utilizing thermal coupling between semiconductor devices, as shown in FIG. 1, has recently been used in an all-stage direct-coupled amplifier. In the all-stage direct-coupled amplifier of FIG. 1, a first stage differential amplifier is comprised of field effect transistors 1 and 2 in order to give a high input impedance characteristic to a power amplifier. The output signal of the first-stage differential amplifier is amplified by a second-stage amplifier 3 including driver and output power stages, and led to an output terminal 4 connected to a load (not shown) such as a loudspeaker. The output terminal 4 is direct-coupled to a feedback input terminal of the first stage differential amplifier, i.e., the gate of the field effect transistor 2. A load of the differential amplifier is a current mirror circuit comprised of bipolar transistors 5 and 6. The transistors 5 and 6 are thermally coupled with transistors 7 and 8 respectively. The bases of transistors 7 and 8 are connected to outputs of a comparator or operational amplifier 9 with one input coupled to the output terminal 4 and the other input coupled to circuit ground, whereby collector currents or junction temperatures of the transistors 7 and 8 are controlled in dependence on the magnitude and polarity of an offset error voltage appearing at the output terminal 4. Thus, the collector currents of transistor 5 and 6 thermal-coupled with the transistors 7 and 8 are controlled to reduce the offset error voltage. This circuit is effective in minimizing the offset voltage since the offset voltage may be regarded as an input-referred offset voltage of the comparator 9.
In the above-mentioned circuit, however, if the collector currents of the transistors 5 and 6 are changed, then the drain currents of FET's 1 and 2 will change to shift their operating points. This will lead to a change in the mutual conductance gm of the FET's and occurrence of distortion.